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audio codec for recordable dvd preliminary technical data adav803 rev. pr g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respectiveorners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features stereo analog to digital converter (adc) supports 48/96 khz sample rates 102 db dynamic range single-ended input automatic level control stereo digital to analog converter (dac) supports 32/44.1/48/96/192 khz sample rates 100 db dynamic range single-ended output asynchronous operation of adc and dac stereo sample rate converter (src) input/output range - 8 - 96 khz 140 db dynamic range digital interfaces record playback aux record aux playback s/pdif (iec60958) input & output digital interface receiver (dir) digital interface transmitter (dit) pll based audio mclk generators generates required dvdr system mclks device control via i 2 c compatible serial port 64-lead lqfp package applications dvd-recordable all formats cd-r/w product overview the adav803 is a stereo audio codec intended for applications, such as dvd or cd recorders, requiring high performance, flexible and cost effective playback and record functionality. the adav803 features analog devices proprietary, high performance converter cores to provide record (adc), playback (dac) and format conversion (src) in a single chip. the adav803's record channel features variable input gain to allow for adjustment of recorded input levels, followed by a high performance stereo adc whose digital output is sent to the record interface. the record channel also features level detectors which can be used in feedback loops to adjust input levels for optimum recording. the playback channel features a high performance stereo dac with independent digital volume control. the sample rate converter (src) provides high performance sample-rate conversion to allow inputs and outputs requiring different sample rates to be matched. the src input can be selected from playback, auxiliary, dir or adc (record). the src output can be applied to the playback dac, both main and auxiliary record channels and a dit. ( continued on page 12 ) functional block diagram analog to digital converter reference src digital to analog converter adav801/2/3/4 dit aux data output record data output control registers pll digital input/output switching matrix (datapath) playback data input aux data input dir vinl vinr vref voutl voutr filtd i l r c l k i b c l k i s d a t a i a u x l r c l k i a u x b c l k i a u x s d a t a d i r i n olrclk obclk osdata oauxlrclk oauxbclk oauxsdata ditout c l a t c h / a d 0 c i n / s d a c c l k / s c l c o u t / a d 1 s y s c l k 3 s y s c l k 2 s y s c l k 1 zerol/int zeror m c l k i x o u t x i n m c l k o figure 1.
adav803 preliminary technical data rev. pr g | page 2 of 54 table of contents specifications..................................................................................... 3 timing specifications....................................................................... 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 functional description .................................................................. 12 adc section ............................................................................... 12 dac section.................................................................................... 15 src functional overview ............................................................. 16 theory of operation .................................................................. 16 conceptual high interpolation model.................................... 16 hardware model......................................................................... 17 the sample rate converter architecture ............................... 17 pll section ................................................................................. 18 spdif transmitter and receiver........................................... 20 serial data ports ......................................................................... 25 clocking scheme........................................................................ 25 interface control ........................................................................ 26 outline dimensions ....................................................................... 54 ordering guide .......................................................................... 54 revision history
preliminary technical data adav803 rev. pr g | page 3 of 54 specifications table 1. test conditions unless otherwise noted supply voltage analog +3.3 v digital +3.3 v ambient temperature 25c master clock (xin) 12.288 mhz measurement bandwidth 20 hz to 20 khz word width (all converters) 24-bits load capacitance on digital outputs 100 pf adc input frequency 997hz at ?1 dbfs dac output frequency 997hz at ?1 dbfs digital input: slave mode, i 2 s justified format digital output: master mode, i 2 s justified forma table 2. pga section min typ max unit conditions input impedance 4 k ? minimum gain 0 db maximum gain 24 db gain step 0.5 db gain step error tbd db table 3. reference section min typ max unit conditions absolute voltage, v ref 1.5 v v ref temperature coefficient tbd ppm/ c table 4. adc s ection 1 min typ max unit conditions number of channels 2 resolution 24 bits dynamic range ?60 db input unweighted 98 100 db a-weighted 99 102 db total harmonic distorton + noise ?85 db input = ?1.0 dbfs analog input input range ( full scale) 1.0 v rms v ref 1.5 v dc accuracy gain error ?1 db interchannel gain mismatch 0.01 db gain drift 100 ppm/c offset tbd mv crosstalk (eiaj method) 100 db volume control step size (256 steps) 0.39 % per step maximum volume attenuation -48 db group delay tbd s 1 the figures quoted are target specificatio ns and subject to change before release
adav803 preliminary technical data rev. pr g | page 4 of 54 table 5. adc low-pass digital decmation filter characteristics 1 sample rate pass band stop band stop band pass band (khz) frequency (khz) frequency (khz) attenuation (db) ripple (db) 48 0.45314 f s 0.54648 f s 120 0.01 96 tbd f s tbd f s tbd tbd 1 guaranteed by design table 6. adc high-pass digital filter characteristics (f s = 48 khz) min typ max units cutoff frequency 0.9 hz table 7. src s e ction min typ max unit conditions resolution 24 bits sample rate 8 96 khz xin = 27mhz maximum sample rate ratios minimum src mclk 138 f s-max f s-max is the greater of the input or output sample rate upsampling 1:8 downsampling 7.75:1 dynamic range 20 hz to f s /2, 1 khz, C60 dbfs input unweighted 120 db worst case - 96 khz:8 khz a-weighted 125 db worst case - 96 khz:8 khz total harmonic distortion + noise ?110 db 20 hz to f s /2, 1 khz, 0 dbfs input table 8. dac s e ction 1 min typ max unit conditions number of channels 2 resolution 24 bits dynamic range (20 hz to 20 khz, ?60 db input) unweighted 98 db a-weighted tbd 101 db a-weighted tbd db f s = 96 khz total harmonic distorton + noise ?96 db digital input = ?1.0 dbfs total harmonic distorton + noise tbd db digital input = ?1.0 dbfs, f s = 96 khz analog outputs output range ( full scale) 1.0 vrms output resistance tbd ? common mode output voltage 1.5 v dc accuracy gain error ?1 db interchannel gain mismatch 0.01 db gain drift 25 ppm/c crosstalk (eiaj method) 125 db phase deviation tbd degrees mute attenuation ?63 db volume control step size (128 steps) 0.5 db group delay tbd s 1 the figures quoted are target specifications and subject to change before release
preliminary technical data adav803 rev. pr g | page 5 of 54 table 9. dac low-pass digital interpolation filter characteristics sample rate pass band stop band stop band pass band (khz) frequency (khz) frequency (khz) attenuation (db) ripple (db) 44.1 0.4535 f s 0.5464 f s 70 0.002 48 0.4541 f s 0.5464 f s 70 0.002 96 0.4161 f s 0.5927 f s 70 0.005 table 10. pll section min typ max unit conditions master clock input frequency 27/54 mhz generated system clocks mclko 27/54 mhz sysclk1 256 768 f s 256/384/512/768 32/44.1/48 khz 1 sysclk2 256 768 f s 256/384/512/768 32/44.1/48 khz 1 sysclk3 256 512 f s 256/512 32/44.1/48 khz 1 jitter sysclk1 tbd ps rms sysclk2 tbd ps rms sysclk3 tbd ps rms 1 sample frequency can be doubled table 11. dir section min typ max unit condition input sample frequency 27.2 220 khz dir-mclk frequency tbd mhz dir-mclk jitter tbd ps differential input voltage tbd mv table 12. dit section min typ max unit condition output sample frequency 27.2 220 khz table 13. digital i/o min typ max unit condition input voltage hi (v ih ) 2.0 dvdd v input voltage lo (v il ) 0.8 v input leakage (i ih @ v ih = 3.3 v) 10 a input leakage (i il @ v il = 0 v) 10 a output voltage hi (v oh @ i oh = 1 ma) 2.4 v output voltage lo (v ol @ i ol = -1 ma) 0.4 v input capacitance 15 pf
adav803 preliminary technical data rev. pr g | page 6 of 54 table 14. power min typ max unit condition supplies voltage, avdd 3.0 3.3 3.6 v voltage, dvdd 3.0 3.3 3.6 v voltage, odvdd 3.0 3.3 3.6 v analog current 45 ma all supplies at 3.6v digital current, dvdd 56 ma all supplies at 3.6v digital interface current, odvdd 12 ma all supplies at 3.6v analog currentpower down tbd a reset low, no mclk digital current - power down tbd a reset low, no mclk digital interface current - power down tbd a reset low, no mclk power supply rejection 1 khz 300 mv p-p signal at analog supply pins tbd db 20 khz 300 mv p-p signal at analog supply pins tbd db stopband (>0.55 f s )any 300 mv p-p signal tbd db
preliminary technical data adav803 rev. pr g | page 7 of 54 timing specifications table 15. parameter min max unit comments master clock and reset f mclk mclki frequency 24.576 mhz f xin xin frequency 54 mhz t reset reset low 20 ns i 2 c port f scl scl clock frequency 400 khz t sclh scl high 0.6 s t scll scl low 1.3 s start condition - t scs setup time 0.6 s relevant for repeated start condition t sch hold time 0.6 s after this period the 1st clock is generated t ds data setup time 100 ns t scr scl rise time 300 ns t scf scl fall time 300 ns t sdr sda rise time 300 ns t sdf sda fall time 300 ns stop condition t scs setup time 0.6 s serial ports 1 slave mode t sbh xbclk high 40 ns t sbl xbclk low 40 ns f sbf xbclk frequency 64 f s t sls xlrclk setup 10 ns to xbclk rising edge t slh xlrclk hold 10 ns from xbclk rising edge t sds xsdata setup 10 ns to xbclk rising edge t sdh xsdata hold 10 ns from xbclk rising edge t sdd xsdata delay 10 ns from xbclk falling edge master mode t mld xlrclk delay 5 ns from xbclk falling edge t mdd xsdata delay 10 ns from xbclk falling edge t mds xsdata setup 10 ns from xbclk rising edge t mdh xsdata hold 10 ns from xbclk rising edge 1 the prefix x refers to i-, o-, iaux- or oaux- for the full pin name table 16. temperature range min typ max units specifications guaranteed 25 c functionality guaranteed ?40 85 c storage ?65 150 c specifications subject to change without notice.
adav803 preliminary technical data rev. pr g | page 8 of 54 absolute maximum ratings table 17. parameter rating dvdd to dgnd and odvdd to dgnd 0 v to 4.6 v avdd to agnd 0 v to 4.6 v digital inputs dgnd ? 0.3 v to dvdd + 0.3 v analog inputs agnd ? 0.3 v to avdd + 0.3 v agnd to dgnd ?0.3 v to +0.3 v reference voltage indefinite short circuit to ground soldering (10 s) +300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data adav803 rev. pr g | page 9 of 54 pin configuration and function descriptions n c v o u t l n c v o u t r o a u x s d a t a i a u x l r c l k i a u x b c l k i a u x s d a t a zerol/int zeror dvdd dgnd advdd adgnd pll_lf2 pll_lf1 pll_gnd pll_vdd dgnd sysclk1 sysclk2 sysclk3 xin xout 39 38 37 41 40 mclko mclki dvdd dgnd 36 35 34 33 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 i l r c l k i b c l k i s d a t a o l r c l k o b c l k o s d a t a d i r i n o d v d d o d g n d d i t o u t o a u x l r c l k o a u x b c l k 1 2 3 4 5 6 7 8 9 10 11 12 64 63 62 61 60 59 58 c a p l n c a p l p a g n d c a p r p c a p r n a v d d a g n d v r e f a g n d f i l t d a g n d a v d d pin 1 identifier top view (not to scale) vinr vinl agnd avdd dir_lf dir_gnd dir_vdd reset ad0 sda scl ad1 13 14 15 16 25 26 27 31 30 29 28 32 57 56 55 54 53 52 51 50 49 adav803 8 0 3 - 0 0 4 5 figure 2. 64-lead plastic quad flatpack [lqfp] (st-520) table 18. adav803 pin function descriptions pin number input/output mnemonic description 1 input vinr analog audio input - right channel 2 input vinl analog audio input - left channel 3 agnd analog ground 4 avdd analog voltage supply 5 dir_lf dir phase locked loop (pll) loop filter pin 6 dir_gnd supply ground for dir analog section. this pin should be connected to agnd 7 dir_vdd supply for dir analog section. this pin should be connected to avdd 8 input reset reset input (active low) 9 input ad0 i 2 c address lsb 10 input/output sda data input/output of i 2 c compatible control interface 11 input scl clock input of i 2 c compatible control interface 12 input ad1 i 2 c address msb 13 output zerol/int left channel (output) zero flag or interrupt (output) flag. the function of this pin is determined by the intrpt bin in dac control register 4 14 output zeror right channel (output) zero flag 15 dvdd digital voltage supply 16 dgnd digital ground 17 input/output ilrclk sampling clock (lrclk) of playback digital input port 18 input/output ibclk serial clock (bclk) of playback digital input port 19 input isdata data input of playback digital input port 20 input/output olrclk sampling clock (lrclk) of record digital output port 21 input/output obclk serial clock (bclk) of record digital output port 22 output osdata data output of record digital output port
adav803 preliminary technical data rev. pr g | page 10 of 54 pin number input/output mnemonic description 23 input dirin input to digital input receiver (s/pdif) 24 odvdd interface digital voltage supply 25 odgnd interface digital ground 26 output ditout s/pdif output from dit 27 input/output oauxlrclk sampling clock (lrclk) of auxiliary digital output port 28 input/output oauxbclk serial clock (bclk) of auxiliary digital output port 29 output oauxsdata data output of auxiliary digital output port 30 input/output iauxlrclk sampling clock (lrclk) of auxiliary digital input port 31 input/output iauxbclk serial (bclk) of auxiliary digital input port 32 input iauxsdata data input of auxiliary digital input port 33 dgnd digital ground 34 dvdd digital supply voltage 35 input mclki external mclk input 36 output mclko oscillator output 37 input xout crystal input 38 input xin crystal or external mclk input 39 output sysclk3 system clock 3 (from pll 2) 40 output sysclk2 system clock 2 (from pll 2) 41 output sysclk1 system clock 1 (from pll 1) 42 dgnd digital ground 43 pll_vdd supply for pll analog section. this pin should be connected to avdd 44 pll_gnd ground for pll analog section. this pin should be connected to agnd 45 pll_lf1 loop filter for pll1 46 pll_lf2 loop filter for pll2 47 adgnd analog ground (mixed signal) 48 advdd analog voltage supply (mixed sign al). this pin should be connected to avdd 49 output voutr right channel analog output 50 nc no connect 51 output voutl left channel analog output 52 nc no connect 53 avdd analog voltage supply 54 agnd analog ground 55 filtd output dac reference decoupling 56 agnd analog ground 57 vref voltage reference voltage 58 agnd analog ground 59 avdd analog voltage supply 60 caprn adc modulator input filter capacitor (right channel - negative) 61 caprp adc modulator input filter capacitor (right channel - positive) 62 agnd analog ground 63 caplp adc modulator input filter capacitor (left channel - positive) 64 capln adc modulator input filter capacitor (left channel - negative)
preliminary technical data adav803 rev. pr g | page 11 of 54 ( continued from page 1 ) operation of the adav803 is controlled via an i 2 c serial interface, which allows individual control register settings to be programmed. the adav803 operates from a single analog +3.3 v power supply - and a digital power supply of +3.3 v with optional digital interface range of 3.0 v to +3.6 v. it is housed in a 64-lead lqfp package and is characterized for operation over the commercial temperature range ?40c to 85c.
adav803 preliminary technical data rev. pr g | page 12 of 54 functional description adc section the adav803's adc section is implemented using a 2 nd order multi-bit (5-bits) sigma-delta modulator. the modulator is sampled at either half the adc mclk rate (modulator clock = 128 f s ) or a quarter of the adc mclk rate (modulator clock = 64 f s ). the digital decimator consists of a sinc^5 filter followed by a cascade of 3 half-band fir filters. the sinc decimates by a factor of 16 at 48 khz and by 8 at 96 khz. each of the half-band filters decimates by a factor of 2. figure 3 below shows the detail of the adc section. the adc can be clocked by a number of different clock sources to control the sample rate. mclk selection for the adc is set by internal clocking control register 1 (address = 0x76). the adc provides an output word of up to 24 bits in resolution in 2s complement format. the output word can be routed to the output ports, to the sample rate converter or to the spdif digital transmitter. xin mclki pll1 internal pll2 internal reg: 0x76 bits 4-2 adc adc mclk dir pll(512 f s ) dir pll(256 f s ) 8 0 1 - 0 0 0 4 adc mclk divider reg: 0x6f bits 1-0 figure 3. clock path control on the adc programmable gain amplifier (pga) the input of the record channel features a pga which converts the single-ended signal to a differential signal which is applied to the analog sigma-delta modulator of the adc. the pga can be programmed to amplify a signal by up to 24db in 0.5db increments. figure 4 details the structure of the pga circuit. 4k ? 4-64k ? 125 ? 125 ? to modulator capxn capxp external capacitor (1nf npo) external capacitor (1nf npo) external capacitor (1nf npo) 8k ? 8k ? vref 8 0 1 - 0 0 0 5 figure 4. pga block diagram analog sigma delta modulator the adc features a 2 nd order, multi-bit, sigma-delta modulator. the input features two integrators in cascade followed by a flash converter. this multi-bit output is directed to a scrambler, followed by a dac for loop feedback. the flash adc output is also converted from "thermometer" coding to "binary" coding for input as a 5-bit word to the decimator. figure 5 shows the adc block diagram. the adc also features independent digital volume control for the left and right channels. the volume control consists of 256 linear steps with each step reducing the digital output codes by 0.39%. each channel also has a peak detector which records the peak level of the input signal. the peak detector register is cleared by reading it. adc modclk multi-bit sigma-delta modulator decimator volume control peak detect hpf halfband filter sinc^5 halfband filter adc mclk/2 (typ 6.144mhz) 384khz 768khz 192khz 384khz sinc compensation 96khz 192khz 48khz 96khz 801-0003 figure 5. adc block diagram
preliminary technical data adav803 rev. pr g | page 13 of 54 selecting a sample rate the sample rate of the adc is always 256 f s . to facilitate different mclks the adc block has a programmable divider which allows the mclk to be divided by 1, 2 or 3 before being applied to the adc. this allows for mclks of 256 f s , 512 f s or 768 f s to be applied to the adc. to synchronize the data output port with the adc the same divider setting should be applied to the internal clock (iclk1 or iclk2) which is controlling the output port. the internal clock dividers are shown in figure 34. by default the ? modulator runs at adc mclk/2. the modulator is designed to run with a maximum clock rate of 6.144mhz,. for cases where higher sample rates would run the modulator at speeds higher than this the user can select divide the adc mclk by 4 before it is applied to the modulator. to compensate for this the modulator uses an alternate filter configuration. the divide setting is selected by the amc bit in adc control register 1.automatic level control (alc) the adc record channel features a programmable automatic level control block. this block monitors the level of the adc output signal and will automatically reduce the gain if the signal at the input pins causes the adc output to exceed a preset limit. this function can be useful to maximize the signal dynamic range when the input level is not well-defined. the pga can be used to amplify the unknown signal and the alc will reduce the gain until the adc output is within the preset limits. this results in maximum front-end gain. since the alc block monitors the output of the adc the volume control function should not be used. the adc volume control scales the results from the adc and any distortion caused by the input signal exceeding the input range of the adc will still be present at the output of the adc but scaled by a value determined by the volume control register. the alc block consists of two functions, attack mode and recovery mode. the recovery mode consists of three settings, namely, no recovery, normal recovery and limited recovery. each of these modes in discussed in detail below. figure 6 shows an overall flow diagram of the alc block. attack mode when the absolute value of the adc output exceeds the level set by the attack threshold bits in the alc control register 2, attack mode is initiated. the pga gain for both channels is reduced by one step (0.5db). the alc will then wait for a time determined by the attack timer bits before sampling the adc output value again. if the adc output is still above the threshold the pga gain is reduced by a further step. this procedure continues until the adc output is below the limit set by the attack threshold bits. the initial gains of the pgas are defined by adc left pga gain register and adc right pga gain register and may be different values. the alc simply adds or subtracts a common gain offset to these values. the alc will preserve any gain difference in db as defined by those registers. at no time will the pga gains exceed their initial values. therefore, the initial gain setting also serves as a maximum value. the limit detection mode bit in alc control register 1 determines how the alc should respond to an adc output which exceeds the set limits. if this bit is a one then both channels must exceed the threshold before the gain is reduced. this mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. if the limit detection mode bit is a zero the gain will be reduced when either channel exceeds the threshold. no recovery mode by default there is no gain recovery. once the gain has been reduced it will not be recovered until the alc has been reset, by toggling the alcen bit in alc control register 1 or by writing any value to alc control register 3. the latter option is more efficient as it requires only one write operation to reset the alc function. no recovery mode prevents volume modulation of the signal, caused by adjusting the gain, which can create undesirable artifacts in the signal. since the gain can be reduced but not recovered, care should be taken that spurious signals do not interfere with the input signal as these may trigger a gain reduction unnecessarily. normal recovery this mode allows for the pga gain to be recovered providing that the input signal meets certain criteria. firstly, the alc must not be in attack mode, i.e., the pga gain has been reduced sufficiently such that the input signal is below the level set by the attack threshold bits. secondly, the output result from the adc must be below the level set by the recovery threshold bits in alc control register. if both of these criteria are met the gain is recovered by one step (0.5db). the gain is incrementally restored to its original value assuming the adc output level is below the recovery threshold at intervals determined by the recovery time bits. should the adc output level exceed the recovery threshold while the pga gain is being restored the pga gain value will be held and will not continue restoration until the adc output level is again below the recovery threshold. once the pga gain is restored to its original value it will not be changed again unless the adc output value exceeds the attack threshold and the alc then enters attack mode. care should be exercised when using this mode to choose values for the attack and recovery thresholds to prevent excessive volume modulation caused by continuous gain adjustments. limited recovery limited recovery mode offers a compromise between no recovery and normal recovery modes. if the output level of the adc exceeds the attack threshold then attack mode is
adav803 preliminary technical data rev. pr g | page 14 of 54 initiated. when attack mode has reduced the pga gain to suitable levels the alc will attempt to recovery the gain to its original level. if the adc output level exceeds the level set by the recovery threshold bits a counter is incremented (gaincntr). this counter is incremented, at intervals equal to the recovery time selection, if the adc has any excursion above the recovery threshold. if the counter reaches its maximum value, determined by the gaincntr bits in alc control register 1, the pga gain is deemed suitable and no further gain recovery is attempted. if, at any time, the adc output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset wait for sample is sample greater than attack threshold? no decrease gain by 0.5db and wait attack time yes is a recovery mode enabled? yes no normal recovery is sample below recovery threshold? wait for sample wait recovery time no increase gain by 0.5db wait recovery time has gain been fully restored? yes no yes is sample below recovery threshold? wait for sample wait recovery time no increase gain by 0.5db wait recovery time has gain been fully restored? yes no yes increment gaincntr is gaincntr at maximum? no yes limited recovery is sample above attack threshold? no is sample above attack threshold? no attack mode 8 0 1 - 0 1 2 7 figure 6. alc flow diagram
preliminary technical data adav803 rev. pr g | page 15 of 54 dac section the adav803 has two dac channels arranged as a stereo pair with single-ended outputs. each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375db per step. the dac can receive data from the playback or auxiliary input ports, the src, the adc or the dir. each analog output pin sits at a dc level of vref, and swings 1.0 vrms for a 0db digital input signal. a single op-amp third-order external low-pass filter is recommended to remove high- frequency noise present on the output pins. note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. the filtd and filtr pins should be bypassed by external capacitors to agnd. the filtd pin is used to reduce the noise of the internal dac bias circuitry, thereby reducing the dac output noise. the voltage at the vref pin, filtr can be used to bias external op amps used to filter the output signals. for applications where the filtr is required to drive external op amps which may draw more than 50a or may have dynamic load changes extra buffering should be used to preserve the quality of the adav803 reference. the digital input data source for the dac can be selected from a number of available sources. by programming the appropriate bits in the datapath control register. figure 7 shows how the digital data source and mclk source for the dac are selected. each dac has an independent volume register giving 256 steps of control with each step giving approximately 0.375db of attenuation. each dac also has a peak level register which records the peak value of the digital audio data. reading the register clears the peak . selecting a sample rate correct operation of the dac is dependant upon the data rate provided to the dac, the master clock applied to the dac and the selected interpolation rate. by default the dac assumes that the mclk rate is 256 times the sample rate which requires an 8 times oversampling rate. this combination is suitable for sample rates up to 48khz. for the case of a 96khz data rate which has a 24.576mhz mclk (256 f s ) associated with it the dac mclk divider should be set to divide the mclk by 2. this will prevent the dac engine being run too fast. to compensate for the reduced mclk rate the interpolator should be selected to operate in 4 (dac mclk = 128 f s ). similar combinations can be selected for different sample rates. xin mclki pll1 internal pll2 internal reg: 0x76 bits 7-5 dac dac mclk auxiliary in playback dir adc reg: 0x63 bits 5-3 dac input dir pll(512 f s ) dir pll(256 f s ) mclk divider reg: 0x65 bits 3-2 801-0007 figure 7. clock and data path control on the dac multi-bit sigma-delta modulator interpolator dac dac to zero flag pins peak detector zero detect from dac datapath multiplexer volume/mute control to control registers analog output 801-0006 figure 8. dac block diagram
adav803 preliminary technical data rev. pr g | page 16 of 54 src functional overview theory of operation asynchronous sample rate conversion is converting data from at the same or different sample rate. the simplest approach to an asynchronous sample rate conversion is the use of a zero- order hold between the two samplers shown in figure 9 in an asynchronous system, t2 is never equal to t1 nor is the ratio between t2 and t1 rational. as a result, samples at fs_out will be repeated or dropped producing an error in the re-sampling process. the frequency domain shows the wide side lobes that result from this error when the sampling of fs_out is convolved with the attenuated images from the sin(x)/x nature of the zero-order hold. the images at fs_in, dc signal images, of the zero-order holdare infinitely attenuated. since the ratio of t2 to t1 is an irrational number, the error resulting from the re- sampling at fs_out can never be eliminated. however, the error can be significantly reduced through interpolation of the input data at fs_in. the sample rate converter in the adav803/ is conceptually interpolated by a factor of 2 20 . zero-order hold in out f s_in =1/t1 f s_out =1/t2 original signal sampled at f s_in sin(x)/x of zer0-order hold spectrum of zero-order hold output spectrum of f s_out sampling 2 f s_out frequency response of fs_out convolved with zero-order hold spectrum f s_out 801-0008 figure 9. zero order hold being used by fs out to resample data from fs_in conceptual high interpolation model interpolation of the input data by a factor of 2 20 involves placing (2 20 ?1) samples between each f s_in sample. figure 10 shows both the time domain and the frequency domain of interpolation by a factor of 2 20 . conceptually, interpolation by 2 20 would involve the steps of zero-stuffing (2 20 ?1) number of samples between each f s_in sample and convolving this interpolated signal with a digital low-pass filter to suppress the images. in the time domain, it can be seen that f s_out selects the closest f s_in 2 20 sample from the zero-order hold as opposed to the nearest f s_in sample in the case of no interpolation. this significantly reduces the re-sampling error. in out f s_in f s_out time domain of f s_in samples time domain output of the low-pass filter time domain of f s_out resampling time domain of the zero-order hold output interpolate by n low-pass filter zero-order hold 8 0 1 - 0 0 0 9 figure 10. src time domain in the frequency domain shown in figure 11, the interpolation expands the frequency axis of the zero-order hold. the images from the interpolation can be sufficiently attenuated by a good low-pass filter. the images from the zero-order hold are now pushed by a factor of 2 20 closer to the infinite attenuation point of the zero-order hold, which is f s_in 2 20 the images at the zero-order hold are the determinin g factor for the fidelity of the output at f s_out . the worst-case images can be computed from the zero-order hold frequency response, maximum image = sin ( f/f s_interp )/( f/f s_interp ). f is the frequency of the worst-case image that would be 2 20 f s_in f s_in /2 , and f s_interp is f s_in 2 20 . the following worst-case images would appear for f s_in = 192 khz: image at f s_interp ? 96 khz = C125.1 db image at f s_interp + 96 khz = C125.1 db
preliminary technical data adav803 rev. pr g | page 17 of 54 frequency domain of samples at f s_in frequency domain of the interpolation frequency domain of f s_out resampling frequency domain after resampling in out f s_in f s_out interpolate by n low-pass filter zero-order hold f s_in 2 20 f s_in sin(x)/x of zer0-order hold 2 20 f s_in 2 20 f s_in 8 0 1 - 0 0 1 0 figure 11. frequency domain of the interpolation and resampling hardware model the output rate of the low-pass filter of figure 10 would be the interpolation rate, 2 20 192000 khz = 201.3 ghz. sampling at a rate of 201.3 ghz is clearly impractical, not to mention the number of taps required to calculate each interpolated sample. however, since interpolation by 2 20 involves zero-stuffing 2 20 ?1 samples between each f s_in sample, most of the multiplies in the low-pass fir filter are by zero. a further reduction can be realized by the fact that since only one interpolated sample is taken at the output at the f s_out rate, only one convolution needs to be performed per f s_out period instead of 2 20 convolutions. a 64-tap fir filter for each f s_out sample is sufficient to suppress the images caused by the interpolation. the difficulty with the above approach is that the correct interpolated sample needs to be selected upon the arrival of f s_out . since there are 2 20 possible convolutions per f s_out period, the arrival of the f s_out clock must be measured with an accuracy of 1/201.3 ghz = 4.96 ps. measuring the f s_out period with a clock of 201.3 ghz frequency is clearly impossible; instead, several coarse measurements of the f s_out clock period are made and averaged over time. another difficulty with the above approach is the number of coefficients required. since there are 2 20 possible convolutions with a 64-tap fir filter, there needs to be 2 20 polyphase coefficients for each tap, which requires a total of 2 26 coefficients. to reduce the amount of coefficients in rom, the src stores small subset of coefficients and performs a high order interpolation between the stored coefficients. so far the above approach works for the case of f s_out > f s_in . however, in the case when the output sample rate, f s_out , is less than the input sample rate, f s_in , the rom starting address, input data, and the length of the convolution must be scaled. as the input sample rate rises over the output sample rate, the anti-aliasing filters cutoff frequency has to be lowered because the nyquist frequency of the output samples is less than the nyquist frequency of the input samples. to move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (f s_in /f s_out ). this technique is supported by the fourier transform property that if f(t) is f( ), then f(k t) is f( /k). thus, the range of decimation is simply limited by the size of the ram. the sample rate converter architecture the architecture of the sample rate converter is shown in figure 12. the sample rate converters fifo block adjusts the left and right input samples and stores them for the fir filters convolution cycle. the f s_in counter provides the write address to the fifo block and the ramp input to the digital servo loop. the rom stores the coefficients for the fir filter convolution and performs a high order interpolation between the stored coefficients. the sample rate ratio block measures the sample rate for dynamically altering the rom coefficients and scaling of the fir filter length as well as the input data. the digital servo loop automatically tracks the f s_in and f s_out sample rates and provides the ram and rom start addresses for the start of the fir filter convolution. right data in left data in fifo rom a rom b rom c rom d high order interp digital servo loop fir filter sample rate ratio f s_in counter sample rate ratio external ratio f s_in f s_out l/r data ou t 801-0011 figure 12. architecture of the sample rate converter the fifo receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the ram. the input data is scaled by the sample rate ratio because as the fir filter length of the convolution increases, so does the amplitude of the convolution output. to keep the output of the fir filter from saturating, the input data is scaled down by multiplying it by (f s_out /f s_in ) when f s_out < f s_in . the fifo also scales the input data for muting and unmuting of the src. the ram in the fifo is 512 words deep for both left and right channels. an offset to the write address provided by the f s_in counter is added to prevent the ram read pointer from ever overlapping the write address. the minimum offset on the src
adav803 preliminary technical data rev. pr g | page 18 of 54 is 16 samples. however, the group delay and mute in register can be used to increase this offset. the number of input samples added to the write pointer of the fifo on the src is 16 + bits 6-0 of the group delay register. this feature is useful in vari- speed applications in order to prevent the read pointer to the fifo running ahead of the write pointer. when set, bit 7 of the group delay and mute in register will soft mute the sample rate. increasing the offset of the write address pointer is useful for applications when small changes in the sample rate ratio between f s_in and f s_out are expected. the maximum decimation rate can be calculated from the ram word depth and the group delay as (512?16)/64 taps = 7.75 for short group delay and (512- 64)/64 taps = 7 for long group delay. the digital servo loop is essentially a ramp filter that provides the initial pointer to the address in ram and rom for the start of the fir convolution. the ram pointer is the integer output of the ramp filter while the rom is the fractional part. the digital servo loop must be able to provide excellent rejection of jitter on the f s_in and f s_out clocks as well as measure the arrival of the f s_out clock within 4.97 ps. the digital servo loop will also divide the fractional part of the ramp output by the ratio of f s_in /f s_out for the case when f s_in > f s_out , to dynamically alter the rom coefficients. the digital servo loop is implemented with a multi-rate filter. to settle the digital servo loop filter more quickly upon startup or a change in the sample rate, a fast mode was added to the filter. when the digital servo loop starts up or the sample rate is changed, the digital servo loop kicks into fast mode to adjust and settle on the new sample rate. upon sensing the digital servo loop settling down to some reasonable value, the digital servo loop will kick into normal or slow mode. during fast mode the mute_out bit in the sample rate error register is asserted to let the user know clicks or pops may be present in the digital audio data. the output of the src can be muted, by asserting bit 7 of the group delay & mute register until the src has changed to slow mode. the mute_out bit can be set to generate an interrupt when the src changes to slow mode indicating that the data will be sample rate converted accurately. the frequency response of the digital servo loop for "fast mode" and "slow mode" are shown in figure 14. the fir filter is a 64-tap filter in the case of f s_out f s_in and is (f s_in /f s_out ) 64 taps for the case when f s_in > f s_out . the fir filter performs its convolution by loading in the starting address of the ram address pointer and the rom address pointer from the digital servo loop at the start of the f s_out period. the fir filter then steps through the ram by decrementing its address by 1 for each tap, and the rom pointer increments its address by the (f s_ou t/f s_in ) 2 20 ratio for f s_in > f s_out or 2 20 for f s_out f s_in . once the rom address rolls over, the convolution is completed. the convolution is performed for both the left and right channels, and the multiply accumulate circuit used for the convolution is shared between the channels. the f s_in /f s_out sample rate ratio circuit is used to dynamically alter the coefficients in the rom for the case when f s_in >f s_out . the ratio is calculated by comparing the output of an f s_out counter to the output of an f s_in counter. if f s_out >f s_in, the ratio is held at one. if f s_in > f s_out , the sample rate ratio is updated if it is different by more than two f s_out periods from the previous f s_out to f s_in comparison. this is done to provide some hysteresis to prevent the filter length from oscillating and causing distortion. iclk1 iclk2 dir pll (256 f s ) dir pll (512 f s ) pllint2 pllint1 mclki xin reg: 0x00 bits 1-0 reg: 0x76 bit 0 reg: 0x76 bit 1 src src mclk auxiliary in playback dir adc reg: 0x62 bits 7-6 src input src output 8 0 1 - 0 0 1 2 figure 13. clock and data path control on the src 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 -210 -220 0.01 0.1 1 10 100 1e3 1e4 1e5 frequency - hz slow mode fast mode m a g n i t u d e - d b 8 0 1 - 0 0 1 3 figure 14. frequency response of the digital servo loop. fs_in is the x-axis, fs_out = 192 khz, master clock is 30 mhz pll section the adav803 features a dual pll configuration to generate independent system clocks for asynchronous operation. figure 17 shows the block diagram of the pll section. the pll generates the internal and system clocks from a 27mhz clock. this clock is generated either by a crystal connected between xin and xout, as shown in figure 15 or from an external
preliminary technical data adav803 rev. pr g | page 19 of 54 clock source connected directly to xin. a 54mhz clock can also be used if the internal clock divider is used. both plls (pll1 and pll2) can be progra mmed independently and cater for a range of sampling rates (32/44.1/48 khz) with selectable system clock oversampling rates of 256 and 384. higher oversampling rates can also be selected by enabling the doubling of the sampling rate to give 512 or 768 f s ratios. note that this option also allows oversampling ratios of 256 or 384 at double sample rates of 64/88.2/96 khz. the pll outputs can be routed internally to act as clock sources for the other component blocks such as the adc, dac etc. the outputs of the plls are also available on the three sysclk pins. figure 18 shows how the plls can be configured to provide the sampling clocks. x i n x o u t c xt a l c 8 0 1 - 0 0 1 7 figure 15. crystal connection table 19. pll frequency selection options pll sample rate mclk selection (f s ) normal f s double f s 1 32/44.1/48 khz 256/384f s 512/768f s 64/88.2/96 khz 256/384f s 2a 32/44.1/48 khz 256/384f s 512/768f s 64/88.2/96 khz 256/384f s 2b same as f s selected 512f s for pll 2a 512f s the plls require a some external components to operate correctly. these components, shown in figure 16 form a loop filter which integrates the current pulses from a charge pump and produces a voltage which is used to tune the vco. good quality capacitors, such as pps film, are recommended .figure 17 shows a block diagram of the pll section including master clock selection. figure 18 shows how the clock frequencies at the clock output pins, sysclk1-3 and the internal pll clock values, pll1 and pll2 are selected. the clock nodes, pll1 and pll2, can be used as master clocks for the other blocks in the adav803 such as the dac or adc. the pll has separate supply and ground pins and these should be as clean as possible to prevent electrical noise being converted into clock jitter by coupling onto the loop filter pins. pll block pll_lfx 33nf 732 ? 1.8nf avdd 8 0 1 - 0 0 1 4 figure 16. pll l f phase detector &loop filter vco n divider output scaler n1 /2 /2 reg: 0x74 bit 4 reg: 0x74 bit 5 phase detector &loop filter vco n divider output scaler n2 output scaler n3 xin xout mclki mclko pll1 pll2 pll_lf1 pll_lf2 sysclk1 sysclk2 sysclk3 reg: 0x78 bit 6 reg: 0x78 bit 7 801-0015 figure 17 . pll section block diagram
adav803 preliminary technical data rev. pr g | page 20 of 54 sysclk1 48 khz 32 khz 44.1 khz reg: 0x75 bit 5 256 384 reg: 0x75 bits 7-6 sysclk2 2 / 2 reg: 0x75 bit 4 reg: 0x77 bits 2-1 / 2 pllint2 sysclk3 pll1 mclk fs2 fs3 pll2 pll2 mclk 48 khz 32 khz 44.1 khz reg: 0x75 bits 3-2 256 384 reg: 0x75 bit 1 2 / 2 pllint1 reg: 0x75 bit 0 reg: 0x77 bit 0 fs1 pll1 801-0016 reg: 0x74 bit 0 256 512 figure 18. pll clocking scheme spdif transmitter and receiver the adav803 contains an integrated spdif transmitter and receiver. the transmitter consists of a single output pin, ditout, on which the biphase encoded data appears. the spdif transmitter source can be selected from the different blocks making up the adav803. additionally the clock source for the spdif transmitter can be selected from the various clock sources available in the adav803. the receiver uses two pins, dirin and dir_lf. dirin accepts the spdif input data stream. the dirin pin can be configured to accept a digital input level as defined by table 13 or an input signal with a peak to peak level of 200mv minimum as defined by the iec60958-3 specification. dir_lf is a loop filter pin required by the internal pll which is used to recover the clock from the spdif data stream. the components shown in figure 22 form a loop filter which integrates the current pulses from a charge pump and produces a voltage which is used to tune the vco of the clock recovery pll. the recovered audio data and audio clock can be routed to the different blocks of the adav801 as required. figure 19 shows a conceptual diagram of the dirin block. dc level c 1 dirin spdif receiver reg: 0x74 bit 4 spdif comparator 801-0128 1 external capacitor is only required for variable level spdif inputs figure 19. dirin block dit auxiliary in playback dir adc reg: 0x63 bits 2-0 dit input src ditout 8 0 1 - 0 0 2 1 figure 20. digital output transmitter block diagram dir audio data dirin recovered clock 801-0022 figure 21. digital input receiver block diagram
preliminary technical data adav803 rev. pr g | page 21 of 54 dir block dir_lf 2.2f 750 ? 82nf avdd + 8 0 1 - 0 0 2 3 figure 22. dir loop filter components serial digital audio transmission standards the adav803 can receive and transmit spdif, aes/ebu and iec-958 serial streams. spdif is a consumer audio standard and aes/ebu is a professional audio standard. iec-958 has both consumer and professional definitions. this data sheet is not intended to fully define or to provide a tutorial for these standards, please contact the international standards setting bodies for the full specifications. all of these digital audio serial communication schemes encode audio data and audio control information using the biphase- mark method. this encoding method minimizes the dc content of the transmitted signal. as can be seen from figure 23 ones in the original data end up with midcell transitions in the biphase- mark encoded data, while zeros in the original data do not. note that the biphase-mark encoded data always has a transition between bit boundaries. 0 11100 clock (2 times bit rate) data biphase-mark data 8 0 1 - 0 0 2 4 figure 23. biphase-mark encoding digital audio communication schemes use preambles to distinguish between channels (called subframes) and between longer term control information blocks (called frames). preambles are particular biphase-mark patterns, which contains encodeing violations that allow the receiver to uniquely recognize them. these patterns, and their relationship to frames and subframes, are shown in figure 24 and figure 25. biphase patterns 11100010 or 00011101 11100100 or 00011011 11101000 or 00010111 left right left and c.s. blockstart channel x y z 8 0 1 - 0 0 2 5 figure 24. biphase-mark encoded preambles left ch xrightch yzleftchrightch yleftch xrightch y sub- frame sub- frame frame 0 frame 1 frame 191 preambles 8 0 1 - 0 0 2 6 figure 25. preambles, frames and subframes the biphase-mark encoding violations are shown in figure 26. note that all three preambles include encoding violations. ordinarily, the biphase-mark encoding method results in a polarity transition between bit boundaries. 1 preamble x 1100010 11100100 preamble y preamble z 11101000 8 0 1 - 0 0 2 8 figure 26. preambles the serial digital audio communication scheme are organized using a frame and subframe construction. there are two subframes per frame (ordinarily the left and right channel). each subframe includes the appropriate four bit preamble, up to 24 bits of audio data, a validity (v) bit, a user (u) bit, a channel status (c) bit and an even parity (p) bit. the channel status bits and the user bits accumulate over many frames to convey control information. the channel status bits accumulate over a 192 frame period (called a channel status block). the user bits accumulate over 1176 frames when the interconnect is implementing the so-called subcode scheme (eiaj cp-2401). the organization of the channel status block, frames and subframes are shown in figure 27 and figure 28. channel status emphasis copy- right non- audio pro/con =0 765432 10 n address category code channel number source number reserved clock accuracy sampling frequency word length reserved reserved n+1 n+2 n+3 n+4 (n+5) to (n+23) data bits n = 0x20 for receiver channel status buffer n = 0x38 for transmitter channel status buffer 8 0 1 - 0 0 2 9 figure 27. consumer
adav803 preliminary technical data rev. pr g | page 22 of 54 sample frequency emphasis lock non- audio pro/con =1 765432 10 n address channel mode alignment level use of auxiliary mode sample bits channel identification digital audio reference signal sample frequency (fs) reserved n+1 n+2 n+3 n+4 n+5 data bits user bit management source word length res- erved fs scaling alphanumeric channel origin data - first character n+6 alphanumeric channel origin data n+7 alphanumeric channel origin data n+8 alphanumeric channel origin data - last character n+9 alphanumeric channel destination data - first character n+10 alphanumeric channel destination data n+11 alphanumeric channel destination data n+12 alphanumeric channel destination data - last character n+13 local sample address code - lsw n+14 local sample address code n+15 local sample address code n+16 local sample address code - msw n+17 timeofdaycode-lsw n+18 time of day code n+19 time of day code n+20 time of day code - msw n+21 reserved n+22 cyclic redundancy check character (crcc_ n+23 reliability flags n = 0x20 for receiver channel status buffer n = 0x38 for transmitter channel status buffer 8 0 1 - 0 0 3 0 figure 28. professional the standards allow for the channel status bits in each subframe to be independent, but ordinarily the channel status bit in the two subframes of each frame are the same. the channel status bits are defined differently for the consumer audio standards and the professional audio standards. the 192 channel status bits are organized into 24 bytes and have the interpretations shown in figure 27 and figure 28. the spdif transmitter and receiver have a comprehensive register set. the registers give the user full access to the functions of the spdif block such as detecting non-audio and validity bits, q subcodes, preambles etc. the channel status bits as defined by the iec60958 and aes3 specification are stored in register buffers for ease of use. an autobuffering function allows for channel status and user bits read by the receiver to be copied directly to the transmitter block removing the need for user intervention. receiver section the adav803 uses a double buffering scheme to handle reading channel status and user bit information. the channel status bits are available as a memory buffer taking up 24 consecutive register locations. the user bits are read using an indirect memory addressing scheme where the receiver user bit indirect address register is programmed with an offset to the user bit buffer and the receiver user bit data register can be read to determine the user bits at that location. reading the receiver user bit data register automatically updates the indirect address register to the next location in the buffer. typically the receiver user bit indirect address register is programmed to zero, the start of the buffer, and the receiver user bit data register is read repeatedly until all the buffers data has been read. figure 29 and figure 30 shows how receiving the channel status and user bits is implemented. spdif receive buffer dirin channel status b (24x8bits) channel status a (24x8bits) receive cs buffer (0x20-0x37) rxcsswitch first buffer second buffer 8 0 1 - 0 0 3 1 figure 29. channel status buffer 0.....7 user bit buffer 8.....15 16.....23 receiver user bit indirect address register receiver user bit data register address = 0x50 address = 0x51 0.....7 first buffer 8.....15 16.....23 spdif in 801-0032 figure 30. receiver user bit buffer the spdif receive buffer is updated continuously by the incoming spdif stream and once all of the channel status bits for the block, 192 for channel a and 192 for channel b, are received the bits are copied into the receiver channel status buffer. this buffer stores all 384 bits of channel status information and the rxcsswitch bit in the channel status switch buffer register determines whether the channel a or channel b status bits are required to be read. the receive channel status bit buffer is 24 bytes long and spans the address range from 0x20 to 0x37. since the channel status bits of an spdif stream rarely change a software interrupt/flag bit, rxcsbint is provided to notify the host control that either a new block of channel status bits is available or that the first 5 bytes of channel status information
preliminary technical data adav803 rev. pr g | page 23 of 54 have changed from a previous block. the function of the rxcsbint is controlled by the rxbconf3 bit in the receiver buffer configuration register. the size of the user bit buffer can be set using by programming the rxbconf0 bit in the receiver buffer configuration register as shown in table 20. table 20. rxbconf3 functionality rxbconf0 receiver user bit buffer size 0 384 bits with preamble z as the start of the block 1 768 bits with preamble z as the start of the block the updating of the user bit buffer is controlled by bits rxbconf2-1 and bits 7 to 4 of the channel status as shown in table 21 and table 22. table 21. rxbconf2-1 functionality rxbconf receiver user bit buffer configuration bit 2 bit 1 0 0 user bits are ignored 0 1 update second buffer when first buffer is full 1 0 format according to byte 1, bits 4-7 if pro bit is set. format according to iec60958-3 if pro bit is clear table 22. automatic user bit configuration bits automatic receiver user bit buffer configuration 7 6 5 4 0 0 0 0 user bits are ignored 0 1 0 0 aes-18 format, the user bit buffer is treated in the same way as when rxbconf2-1 = 0b01 1 0 0 0 user bit buffer is updated in the same way as when rxbconf2-1 = 0b01 and rxbconf0 = 0b00 1 1 0 0 user defined format, the user bit buffer is treated in the same way as when rxbconf2-1 = 0b01 when the user bit buffer has been filled, the rxubint interrupt bit in the interrupt status register will be set, provided that the rxubint mask bit is set, to indicate that the buffer has new information and can be read. for the special case when the user data is formatted according to the iec60958-3 standard into messages made of of information units, called ius, the zeros stuffed between each iu and each message are removed and only the ius are stored. once the end of the message is sensed, by more that 8 zeros between ius, the user bit buffer is updated with the complete message and the first buffer begins looking for the start of the next message. each iu is stored as a byte consisting of 1, q, r, s, t, u, v and w bits (see the iec60958-3 specification for more information). for the case where 96ius are received, the q subcode of the ius is stored in the q subcode buffer consisting of 10 bytes. the q subcode is the q bits taken from each of the 96 ius. the first 10 bytes, 80 bits, of the q subcode contain information sent by cd, md and dat systems. the last 16 bits of the q subcode are used to perform a crc check of the q subcode. if an error occurs in the crc check of the q subcode, the qcrcerror bit will be set. this is a sticky bit and will remain high until the register is read. transmitter operation the spdif transmitter has a similar buffer structure to the receive section. the transmitter channel status buffer occupies 24 bytes of the register map. this buffer is long enough to store the 192 bits required for one channel of channel status information. setting the txcsswitch bit determines if the data loaded to the transmitter channel status buffer is intended for channel a or channel b. in most cases the channel status bits for channel a and channel b are the same in which case setting the tx_a/b_same bit will read the data from the transmitter channel status buffer and transmit it on both channels. since the channel status information is rarely changed during transmission the information contained in the buffer is transmitted repeatedly. the disable_tx_copy bit can be used to prevent the channel status bits from being copied from the transmitter cs buffer into the spdif transmitter buffer until the user has finished loading the buffers. this feature is typically used if the channel a and channel b data is different. setting the bit will prevent the data being copied and clearing the bit will allow the data to be copied and then transmitted. figure 31 shows how the buffers are organized. spdif transmit buffer ditout channel status b (24x8bits) channel status a (24x8bits) transmit cs buffer (0x38-0x4f) txcsswitch 8 0 1 - 0 0 3 3 figure 31. transmitter channel status buffer as with the receiver section the transmitted user bits are also double buffered. this is required since, unlike the channel status bits, the user bits do not necessarily repeat themselves. the user bits can be buffered in various configuration as table 23. transmission of the user bits is determined by the state of the bconf3 bit. if the bit is 0 the user bits will begin transmitting straight away without alignment to the z preamble. if this bit is 1 the user bits will not start transmitting until a z preamble occurs when the txbconf2-1 bits are 01.
adav803 preliminary technical data rev. pr g | page 24 of 54 table 23. transmitter user bit buffer configurations txbconf2- 1 transmitter user bit buffer configuration bit2 bit1 0 0 zeros are transmitted for the user bits 0 1 host writes user bits to the buffer until it is full 1 0 write the user bits to the buffer in ius specified by iec60958-3 and transmit them according to the standard 1 1 the first 10 bytes of the user bit buffer is configured to store a q subcode table 24. transmitter user bit buffer size txbconf0 buffer size 0 384 bits with preamble z as the start of the block 1 768 bits with preamble z as the start of the block the transmit buffers can notify the host or micro-controller when the first user bit buffer has been updated and when the second transmit user bit buffer is full using sticky bits and interrupts. the sticky bit txubint, is set when the transmit user buffer has been updated and the second transmit user bit buffer is ready to accept new user bits. the sticky bit, txfbint, is set whenever the second transmit user bit buffer is full and any new writes to this buffer will be ignored until the first transmit buffer is updated. these two bits are located in the interrupt status register. when the host reads the interrupt status register these bits will be cleared. interrupts for the txubint and txfbint sticky bits can be enabled by setting the txubmask and txfbmask bits respectively in the interrupt status mask register. 0.....7 user bit buffer 8.....15 16.....23 transmitteruserbit indirect address register transmitter user bit data register address = 0x52 address = 0x53 0.....7 second buffer 8.....15 16.....23 spdif out 8 0 1 - 0 0 3 4 figure 32.transmitter user bit buffer autobuffering the adav803 spdif receiver and transmitter sections have an autobuffering mode allowing the channel status and user bits to be copied automatically from the receiver to the transmitter without user intervention. the channel status and user bits can be independently selected for autobuffering using the auto_csbits and auto_ubits bits in autobuffer register respectively. when the receiver and transmitter are running at the same sample rate the transmitted channel status and user bits will be the same as the received channel status and user bits. however in many systems it is likely that the receiver and transmitter will not be running at the same frequency. when the transmitter sample rate is higher than receiver sample rate, the channel status and user bit block may be repeated sometimes. when the transmitter sample rate is lower than the receiver sample rate, the channel status and user bit blocks may be dropped. since the first 5 bytes of the channel status are, typically, constant the can be repeated or dropped and no information is lost. however, if the pro bit in the channel status is set and the local sample address code and time of day code bytes contain information, these bytes may be repeated or dropped in which case information can be lost. it is up to the user to determine how to handle this case. in the case of the user bits being transmitted according to the iec60958-3 format the messages contained in the user bits can still be sent without dropping or repeating messages. since zero-stuffing is allowed between ius and messages, zeros can be added or subtracted to preserve the messages. for the case when the transmitter sample rate is greater than the receiver sample rate extra zeros are stuffed between the messages. when the sample rate of the transmitter is less than the sample rate of the receiver, the zeros stuffed between the messages will be subtracted. if there is not enough zeros between the messages to be subtracted, the zeros between ius will be subtracted as well. the zero_stuff_iu bit in the autobuffer register enables zeros to be added or subtracted between messages. interrupts the adav803 provides interrupt bits to indicate the presence of certain conditions which may require attention. reading the interrupt status register will allow the user to determine if any of the interrupts have be asserted. the bits of the interrupt status register will remain high, if set, until the register is read. two bits, srcerror and rxerror indicate interrupt conditions in the sample rate converter and an spdif receiver error respectively. both of these condition require a read of the appropriate error register to determine the exact cause of the interrupt. each interrupt in the interrupt status register has an associated mask bit in the interrupt status mask register. the interrupt mask bit must be set for the corresponding interrupt to be generated. this feature allows the user to determine which functions should be responded to. the dual function pin zerol/int can be set to indicate the presence of no audio data on the left channel or the presence of an interrupt being set in the interrupt status register. the function of this pin is selected by the intrpt bit in dac control register 4 as shown in table 25.
preliminary technical data adav803 rev. pr g | page 25 of 54 table 25. zerol/int pin functionality intrpt pin functionality 0 the pin functions as a zerol flag pin 1 the pin functions as an interrupt pin serial data ports the adav803 contains four flexible serial ports (sports) to allow data transfer to and from the codec. all four sports are independent and can be configured as master or slave ports. in slave mode the xlrclk and xbclk signals are inputs to the serial ports. in master mode, the serial port generates the xlrclk and xbclk signals. the master clock for the sport can be selected from a number of sources, as shown in figure 34 and care should be taken to ensure that the clock rate is appropriate for whatever block is connected to the serial port. for example if the adc is running from the mclki input at 256 f s then the master clock for the sport should also run run from the mclki input to ensure that the adc and serial port are synchronised. . the sports can be set to transmit or receive data in i 2 s, left justified or right justified formats with different word lengths by programming the appropriate bits in the playback, auxiliary input port, record and auxiliary output port control registers. figure 33 shows a timing diagram of the serial data port formats. clocking scheme the adav803 provides a flexible choice of on-chip and off- chip clocking sources. the on-chip oscillator with dual-plls is intended to offer complete system clocking requirements for use with available mpeg encoders, decoders or combination codecs. the oscillator function is designed for generation of a 27 mhz video clock from a 27 mhz crystal connected between xin and xout pins. capacitors are also required to be connected between these pins and dgnd as shown in figure 15. the capacitor values should be specified by the crystal manufacturer. a square-wave version of the crystal clock is output on the mclko pin. if the system has 27mhz clock available this can be connected directly to the xin pin. data path the adav803 features a digital input/output switching/multiplexing matrix which gives flexibility to the range of possible input and output connections. digital input ports include playback and auxiliary input - both 3-wire digital - and s/pdif (single wire to the on-chip receiver). output ports include the record and auxiliary output ports - both 3-wire digital - and the s/pdif port (single wire from the on-chip transmitter). internally the dir and dit are interfaced via 3- wire interfaces. the data path for each input and output port is selected by programming datapath control registers 1 and 2. figure 35 shows the internal data path structure of the adav803. lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata left channel right channel left channel right channel left channel right channel msb msb msb msb msb msb lsb lsb lsb lsb lsb lsb left-justified mode - 16 bits to 24 bits per channel i 2 s mode - 16 bits to 24 bits per channel right-justified mode - select number of bits per channel 8 0 1 - 0 0 1 8 figure 33. serial data modes
adav803 preliminary technical data rev. pr g | page 26 of 54 pllint1 pllint2 iclk1 mclki xin iclk2 reg: 0x76 bits 4-2 dir pll (512 f s ) dir pll (256 f s ) pllint1 pllint2 mclki xin adc mclk output port olrclk obclk osdata dir pll (512 f s ) dir pll (256 f s ) pllint1 pllint2 mclki xin reg: 0x76 bits 7-5 dac mclk reg: 0x77 bits 4-3 reg: 0x76 bits 1-0 dir pll (512 f s ) dir pll (256 f s ) reg: 0x00 bit 1-0 src mclk input port ilrclk ibclk isdata iclk1 iclk2 pll clock reg:0x04 bits 4-3 iclk1 iclk2 reg:0x06 bits 4-3 pll clock mclki xin pllint1 pllint2 8 0 1 - 0 0 1 9 divider divider reg: 0x00 bits 4-5 reg: 0x00 bits 3-2 divider reg: 0x00 bits 1-0 figure 34. sport clocking scheme adc src dac playback data input aux data input dir dit aux data output record data output control registers reference oscillator pll 8 0 1 - 0 0 2 0 figure 35. data path interface control the adav803 has a dedicated control port to allow the internal registers of the adav803 to be accessed. each of the internal registers is 8 bits wide. where bits are described as reserved (res) these bits should be programmed as zero. i 2 c interface the i 2 c interface of the adav803 is a two wire interface consisting of a clock line, scl and a data line, sda. sda is bidirectional and the adav803 will drive sda either to acknowledge the master, ack, or to send data during a read operation. the sda pin for the i 2 c port is an open drain collector and requires a 1k? pullup resistor. a write or read access occurs when the sda line is pulled low while the scl line is high indicated by start in the timing diagrams. sda is only allowed to change when scl is low except when a start or stop condition occurs as shown in figures 36 and 37. the first eight bits of the access consist of the device address and the r/w bit. the device address consists of an internal built-in address (0b00100) and two address pins, ad1 and ad0. the two address pins allow up to four adav803s to be used in a system. initiating a write operation to the adav803 involves sending a start condition and then sending the device address with the r/w set low. the adav803 will respond by issuing an ack to indicate that it has been addressed. the user
preliminary technical data adav803 rev. pr g | page 27 of 54 then sends a second frame telling the adav803 which register is required to be written to. the 7 bit register address is left shifted to make the 8 bits that the frame requires. another ack is issued by the adav803. finally the user can send another frame with the 8 data bits required to be written to the register. a third ack is issued by the adav803 after which the user can send a stop condition to complete the data transfer. a read operation requires that the user first write to the adav803 to point to the correct register and then read the data. this is achieved by sending a start condition followed by the device address frame, with r/w low, and then the register address frame. following the ack from the adav803 the user must issue a repeated start condition. this is identical to a start condition. the next frame is the device address with r/w set high. on the next frame the adav803 will output the register data on the sda line. a stop condition completes the read operation. figure 38 and figure 39 show examples of writing to and reading from the dac left volume register (address = 0b1101000) r/ w 0 sck sda 0 1 0 0 ad1 ad0 1 1 0 1 0 0 0 x ack. by adav803 start by master d7 d6 d5 d4 d3 d2 d1 d0 ack. by adav803 stop by master sck (continued) sda (continued) frame 1 chip address byte frame 3 data byte to adav803 frame 2 register address byte ack. by adav803 8 0 3 - 0 0 3 9 figure 38. writing to the adav803 ini 2 c r/ w 0 scl sda 0 1 0 0 ad1 ad0 1 1 0 1 0 0 0 x ack. by adav803 start by master d7 d6 d5 d4 d3 d2 d1 d0 ack. by adav803 stop by master frame 1 chip address byte frame 2 register address byte ack. by adav803/4 r/ w 0 scl (continued) sda (continued) 01 0 0 ad1 ad0 repeated start by master frame 3 chip address byte frame 4 register data ack. by adav803/4 8 0 3 - 0 0 4 0 figure 39. reading from the dac leeft volumeregister in i 2 c block reads and writes the adav803 provides the user with the ability to write to or read from a block of registers in one continuous operation. to use this feature the user simply has to continue providing data frames before the stop condition. for a write operation the register address is automatically incremented with each additional frame and the register data is written to that register address. for a read operation the register address is automatically incremented with each additional frame and the register data is clocked out on that frame. care should be exercised when using the block read or block write modes. for most cases block reading, or writing to, a register will automatically increment the register address to point to the next register. the exceptions to this case are the indirect memory address registers, transmitter user bit and receiver user bit
adav803 preliminary technical data rev. pr g | page 28 of 54 data buffers. using a block read or write to access these registers will not update the absolute register address but rather will update the buffer address to provide the next value in the buffer.
preliminary technical data adav803 rev. pr g | page 29 of 54 table 26. src & clock control register clk2- clk2- clk1- clk1- mclk- mclk- srcdiv1 srcdiv div1 div0 div1 div0 sel1 sel0 7 6 5 4 3 2 1 0 address = 0000000 srcdiv1-0 divides the src master clock 00 = the src master clock is not divided 01 = the src master clock is divided by 1.5 10 = the src master clock is divided by 2 11= the src master clock is divided by 3 clk2div1-0 clock divider for internal clock 2 (iclk2) 00 = divide by 1 01 = divide by 1.5 10 = divide by 2 11 = divide by 3 clk1div1-0 clock divider for internal clock 1 (iclk1) 00 = divide by 1 01 = divide by 1.5 10 = divide by 2 11 = divide by 3 mclksel1-0 clock selection for the src master clock 00 = internal clock 1 01 = internal clock 2 10 = pll recovered clock (512 f s ) 11 = pll recovered clock (256 f s ) table 27. spdif loopback control register res res res res res res res txmux 7 6 5 4 3 2 1 0 address = 0000011 txmux selects the source for spdif output (ditout) 0 = spdif transmitter - normal mode 1 = dirin - loopback mode
adav803 preliminary technical data rev. pr g | page 30 of 54 table 28. playback port control register res res res clksrc1 clksrc0 spmode2 spmode1 spmode0 7 6 5 4 3 2 1 0 address = 0000100 clksrc1-0 selects the clock source for generating the ilrclk and ibclk 00 = input port is a slave 01 = recovered pll clock 10 = internal clock 1 11 = internal clock 2 spmode1-0 selects the serial format of the playback port 000 = left justified 001 = i 2 s 100 = 24 bit right justified 101 = 20 bit right justified 110 = 18 bit right justified 111 = 16 bit right justified table 29. auxiliary input port register res res res clksrc1 clksrc0 spmode2 spmode1 spmode0 7 6 5 4 3 2 1 0 address = 0000101 clksrc1-0 selects the clock source for generating the iauxlrclk and iaxubclk 00 = input port is a slave 01 = recovered pll clock 10 = internal clock 1 11 = internal clock 2 spmode1-0 selects the serial format of auxiliary input port 000 = left justified 001 = i 2 s 100 = 24 bit right justified 101 = 20 bit right justified 110 = 18 bit right justified 111 = 16 bit right justified
preliminary technical data adav803 rev. pr g | page 31 of 54 table 30. record port control register res res clksrc1 clksrc0 wlen1 wlen0 spmode1 spmode0 7 6 5 4 3 2 1 0 address = 0000110 res reserved clksrc1-0 selects the clock source for generating the olrclk and obclk 00 = record port is a slave 01 = recovered pll clock 10 = internal clock 1 11 = internal clock 2 wlen1-0 selects the serial output word length 00 = 24 bits 01 = 20 bits 10 = 18 bits 11 = 16 bits spmode1-0 selects the serial format of the record port 00 = left justified 01 = i 2 s 10 = reserved 11 = right justified table 31. auxiliary output port register res res clksrc1 clksrc0 wlen1 wlen0 spmode1 spmode0 7 6 5 4 3 2 1 0 address = 0000111 res reserved clksrc1-0 selects the clock source for generating the oauxlrclk and oauxbclk 00 = auxiliary record port is a slave 01 = recovered pll clock 10 = internal clock 1 11 = internal clock 2 wlen1-0 selects the serial output word length 00 = 24 bit 01 = 20 bits 10 = 18 bits 11 = 16 bits spmode1-0 selects the serial format of the auxiliary record port 00 = left justified 01 = i 2 s 10 = reserved 11 = right justified
adav803 preliminary technical data rev. pr g | page 32 of 54 table 32. group delay and mute register mute_src grpdly6-0 7 6,5,4,3,2,1,0 address = 0001000 mute_src soft mutes the output of thesample rate converter 0 = no mute 1 = soft mute grpdly6-0 adds delay to the sample rate converter fir filter by grpdly6-0 input samples 0000000 = no delay 0000001 = 1 sample delay 0000010 = 2 sample delay 1111110 = 126 sample delay 1111111 = 127 sample delay table 33. receiver configuration 1 register no- clock rxclk1-0 auto_ deemph err1-0 lock1-0 7 6,5 4 3,2 1,0 address = 0001001 noclock selects the source of the receiver clock when the pll is not locked 0 = the recovered pll clock is used 1 = iclk1 is used rxclk1-0 determines the oversampling ratio of the recovered receiver clock 00 = rxclk is a 128 f s recovered clock 01 = rxclk is a 256 f s recovered clock 10 = rxclk is a 512 f s recovered clock 11 = reserved auto_deemph automatically de-emphasizes the data from the receiver based on the channel status information 0 = automatic de-emphasis is disabled 1 = automatic de-emphasis is enabled err1-0 defines what action the receiver should take if the receiver detects a parity or biphase error 00 = no action will be taken 01 = the last valid sample is held 10 = the invalid sample is replaced with zeros 11 = reserved lock1-0 defines what action the receiver should take if the pll loses lock. 00 = no action will be taken 01 = the last valid sample will be held 10 = zeros will be sent out after the last valid sample 11 = soft mute of the last valid audio sample
preliminary technical data adav803 rev. pr g | page 33 of 54 table 34. receiver configuration 2 register sp_pll_ no non- no_ rxmute sp-pll sel1-0 res res audio validity 7 6 5,4 3 2 1 0 address = 0001010 rxmute hard mutes the audio output for the aes3/spdif receiver 0 = aes3/spdif receiver is not muted 1 = aes3/spdif receiver is muted sp_pll the aes3/spdif receiver pll will accept a left/right clock from one of the four serial ports as the pll reference clock 0 = left/right clock generated from the aes3/spdif preambles is the reference clock to the pll 1 = left/right clock from one of the serial ports is the reference clock to the pll sp_pll_sel1-0 selects one of the four serial ports as the refe rence clock to the pll when sp_pll is set 00 = playback port is selected 01 = auxiliary input port is selected 10 = record port is selected 11 = auxiliary output port is selected no nonaudio when the nonaudio bit is set, data from the aes3/spdif receiver will not be allowed into the sample rate converter (src). if the nonaudio data is due to dts, aac, etc. as defined by the iec61937 standard, then the data from the aes3/spdif receiver will not be allowed into the src regardless of the state of this bit 0 = aes3/spdif receiver data will be sent to the src 1 = data fro the aes3/spdif receiver will not be allowed into the src if the nonaudio bit is set no_validity when the validity bit is set data from the aes3/spdif receiver will not be allowed into the src 0 = aes3/spdif receiver data will be sent to the src 1 = data from the aes3/spdif receiver will not be allowed into the src if the validity bit is set table 35. receiver buffer configuration register res res rxbconf5 rxbconf4 rxbconf3 rxbconf2-1 rxbconf0 7 6 5 4 3 2,1 0 address = 0001011 rxbconf5 if the user bits are formatted according to the iec60958-3 standard and the dat category is detected, the user bit interrupt is only enabled when there is a change in the start (id) bit. 0 = the user bit interrupt is enabled in the normal mode. 1 = if the dat category is detected, the user bit interrupt is only enabled if there is a change in the start (id) bit rxbconf4 this bit determines whether channel a and channel b user bits are stored in the buffer together or separated between a and b 0 = the user bits are stored together 1 = the user bits are stored separately rxbconf3 defines the function of rxcsbint 0 = rxcsbint will be set when a new block of receiver channel status is read, which is 192 audio frames 1 = rxcsbint will be set only if the first five bytes of the receiver channel status block changes from the previous channel status block rxbconf2-1 defines the user bit buffer 00 = user bits are ignored 01 = update the second user bit buffer when the first user bit buffer is full 10 = format the received user bits according to byte 1, bits 4-7, of the channel status if the pro bit is set. if the pro bit is not set format the user bits according to the iec60958-3 standard 11 = reserved rxbconf0 defines the user bit buffer size if rxbconf2-1 = 01 0 = 384 bits with preamble-z as the start of the buffer 1 = 768 bits with preamble-z as the start of the buffer
adav803 preliminary technical data rev. pr g | page 34 of 54 table 36. transmitter control register res tx-validity tx-ratio2-0 txclk sel1-0 tx-enable 7 6 5,4,3 2,1 0 address = 0001100 txvalidity this bit is used to set or clear the validity bit in the aes3/spdif transmit stream 0 = audio is suitable for d/a conversion 1 = audio is not suitable for d/a conversion txratio2-0 determines the aes3/spdif transmit to aes3/spdif receiver ratio 000 = transmitter to receiver ratio is 1:1 001 = transmitter to receiver ratio is 1:2 010 = transmitter to receiver ratio is 1:4 101 = transmitter to receiver ratio is 2:1 110 = transmitter to receiver ratio is 4:1 txclksel1-0 selects the clock source for the aes3/spdif transmitter 00 = internal clock 1 is the clock source for the transmitter 01 = internal clock 2 is the clock source for the transmitter 10 = the recovered pll clock is the clock source for the transmitter 11 = reserved txenable enables the aes3/spdif transmitter 0 = the aes3/spdif transmitter is disabled 1 = the aes3/spdif transmitter is enabled table 37. transmitter buffer configuration register iu_zeros3-0 txbconf3 txbconf2-1 txbconf0 7,6,5,4 3 2,1 0 address = 0001101 iu_zeros3-0 determines the number of zeros to be stuffed between ius in a message up to a maximum of 8 0000 = 0 0001 = 1 ...... 0111 = 7 1000 = 8 txbconf3 the transmitter user bits can be stored in separate buffers or stored together 0 = the user bits are stored together 1 = the user bits are stored seperately txbconf2-1 configures the transmitter user bit buffer. 00 = zeros are transmitted for the user bits 01 = the transmitter user bit buffer size is configured according to txbconf0 10 = write the user bits to the transmit buffer in ius specified by the iec60958-3 standard 11 = reserved txbconf0 determines the buffer size of the transmitter user bits when txbconf2-1 is 01 0 = 384 bits with preamble-z as the start of the buffer 1 = 768 bits with preamble-z as the start of the buffer
preliminary technical data adav803 rev. pr g | page 35 of 54 table 38. channel status switch buffer and transmitter tx_a/b disable_ res res same tx_copy res res txcsswitch rxcsswitch 7 6 5 4 3 2 1 0 address = 0001110 tx_a/b_same transmitter channel status a and b are the same. the transmitter will only read from the channel status a buffer and place the data into the channel status b buffer 0 = channel status for a and b are separate 1 = channel status for a and b are the same disable_tx_copy disables the copying of the channel status bits from transmitter channel status buffer to spdif transmitter buffer 0 = copying transmitter channel status is enabled 1 = copying transmitter channel status is disabled res reserved res reserved txcsswitch the toggle switch for the transmit channel status buffer 0 = the 24 byte transmitter channel status a buffer can be accessed at address locations 0x38 through 0x4f 1 = the 24 byte transmitter channel status b buff er can be accessed at address locations 0x38 through 0x4f rxcsswitch the toggle switch for the receive channel status buffer 0 = the 24 byte receiver channel status a buffer can be accessed at address locations 0x20 through 0x37 1 = the 24 byte receiver channel status b buffer can be accessed at address locations 0x20 through 0x37 table 39. transmitter message zeros most significant byte msbzeros7-0 7,6,5,4,3,2,1,0 address = 0001111 msbzero7-0 the most significant byte of the number of zeros to be stuffed between iec60958-3 messages (packets) default = 0x00 table 40. transmitter message zeros least significant byte lsbzeros7-0 7,6,5,4,3,2,1,0 address = 0010000 lsbzero7-0 the least significant byte of the number of zeros to be stuffed between iec60958-3 messages (packets) default = 0x09
adav803 preliminary technical data rev. pr g | page 36 of 54 table 41. autobuffer register res zero_stuff_iu auto_ubits auto_csbits iu_zeros3-0 7 6 5 4 3,2,1,0 address = 0010001 zero_stuff_iu enables the addition or subtraction of zeros between ius during autobuffering of the user bits in iec60958-3 format 0 = no zeros added or subtracted 1 = zeros can be added or subtracted between ius auto_ubits enables the user bits to be autobuffered between the aes3/spdif receiver and transmitter 0 = the user bits are not autobuffered 1 = the user bits are autobuffered auto_csbits enables the channel status bits to be autobuffered between the aes3/spdif receiver and transmitter 0 = the channel status bits are not autobuffered 1 = the channel status bits are autobuffered iu_zeros3-0 sets the maximum number of zero stuffing to be added between ius while autobuffering up to a maximum of 8 0000 = 0 0001 = 1 ...... 0111 = 7 1000 = 8 table 42. sample rate ratio msb register (read only) res srcratio14-srcratio08 7 6,5,4,3,2,1,0 address = 0010010 srcratio14-08 the seven most significant bits of the fifteen bit sample rate ratio table 43. sample rate ratio lsb register (read only) srcratio07-srcratio01 7,6,5,4,3,2,1,0 address = 0010011 srcratio07-00 the eight least significant bits of the fifteen bit sample rate ratio table 44. preamble-c msb register (read only) pre_c15-pre_08 7,6,5,4,3,2,1,0 address = 0010100 pre_c15-08 the eight most significant bits of the sixteen bit preamble-c when nonaudio data is detected according to the iec60937 standard, otherwise bits show zeros table 45. preamble-c lsb register (read only) pre_c07-pre_c00 7,6,5,4,3,2,1,0 address = 0010101 pre_c07-00 the eight least significant bits of the sixteen bit preamble-c when nonaudio data is detected according to the iec60937 standard, otherwise bits show zeros
preliminary technical data adav803 rev. pr g | page 37 of 54 table 46. preamble-d msb register (read only) pre_d15-pre_d08 7,6,5,4,3,2,1,0 address = 0010110 pre_d15-08 the eight most significant bits of the sixteen bit preamble-d when nonaudio data is detected according to the iec60937 standard, otherwise bits show zeros. when subframe nonaudio is used this becomes the 8 most significant bits of the 16 bi t preamble-c of channel b table 47. preamble-d lsb register (read only) pre_d07-pre_d00 7,6,5,4,3,2,1,0 address = 0010111 pre_d07-00 the eight least significant bits of the sixteen bit preamble-d when nonaudio data is detected according to the iec60937 standard, otherwise bits show zeros when subframe nonaudio is used this becomes the 8 most significant bits of the 16 bit preamble-c of channel b table 48. receiver error register (read only) non- nonaudio crc- no- biphase/ rxvalidity emphasis audio preamble error stream parity lock 7 6 5 4 3 2 1 0 address = 0011000 rxvalidity this is the validity bit in the aes3 received stream emphasis this bit will be set if the audio data is preemphasized. once it has been read it will remain high and not generate an interrupt unless it changes state nonaudio this bit will be set when channel status bit 1 (nonaudio) is set. once it has been read it will not generate another interrupt unless the data becomes audio or the type of nonaudio data changes nonaudio preamble this bit will be set if the audio data is nonaudio due to the detection of a preamble. the nonaudio preamble type register will indicate what type of preamble was detected. once read it will remain in its state and not generate an interrupt unless it has changed state crcerror this bit is the error flag for the channel status crc error check. this bit will not clear until the receiver error register is read nostream this bit will be set if there is no aes3/spdif stream present at the aes3/spdif receiver. once read it will remain high and not generate an interrupt unless its changes state. biphase/parity this bit will be set if a biphase or parity error occu rred in the aes3/spdif stream. this bit will not be cleared until the register is read. lock this bit will be set if the pll has locked or cleare d when the pll loses lock. once read it will remain in its state and not generate an interrupt unless it has changed state.
adav803 preliminary technical data rev. pr g | page 38 of 54 table 49. receiver error mask register nonaudio crc biphase/ rxvalidity emphasis nonaudio preamble error nostream parity lock mask mask mask mask mask mask mask mask 7 6 5 4 3 2 1 0 address = 0011001 rxvalidity mask masks the rxvalidity bit from generating an interrupt 0= the rxvalidity bit will not generate an interrupt 1 = the rxvvalidity bit will generate and interrupt emphasis mask masks the emphasis bit from generating an interrupt 0 = the emphasis bit will not generate an interrupt 1 = the emphasis bit will generate and interrupt nonaudio mask masks the nonaudio bit from generating an interrupt 0 = the nonaudio bit will not generate an interrupt 1 = the nonaudio bit will generate and interrupt nonaudiopreamble mask masks the nonaudio preamble bit from generating an interrupt 0 = the nonaudio preamble bit will not generate an interrupt 1 = the nonaudio preamble bit will generate and interrupt crcerror mask masks the crc error bit from generating an interrupt 0 = the crc error bit will not generate an interrupt 1 = the crc error bit will generate and interrupt nostream mask masks the nostream bit from generating an interrupt 0 = the nostream bit will not generate an interrupt 1 = the nostream bit will generate an interrupt biphase/parity mask masks the biphase/parity bit from generating an interrupt 0 = the biphase/parity bit will not generate an interrupt 1 = the biphase/parity bit will generate an interrupt lock mask masks the lock bit from generating an interrupt 0 = the lock bit will not generate an interrupt 1 = the lock bit will generate an interrupt table 50. sample rate converter error register (read only) res res res res too_slow ovrl ovrr mute_ind 7 6 5 4 3 2 1 0 address = 0011010 too_slow this bit is set when the clock to the src is too slow, i.e. there are not enough clock cycles to complete the internal convolution. ovrl this bit will be set when the left output data of the sample rate converter has gone over the full-scale range and has been clipped. this bit will not be cleared until the register is read. ovrr this bit will be set when the right output data of the sample rate converter has gone over the full-scale range and has been clipped. this bit will not be cleared until the register is read. mute_ind mute indicated. this bit is set when the src is in fast mode and clicks or pops may be heard in the src output data. the output of the src can be muted, if required, until the src is in slow mode. once read this bit will remain in its state and not generate an interrupt until it has changed state.
preliminary technical data adav803 rev. pr g | page 39 of 54 table 51. sample rate converter error mask register res res res res res ovrl mask ovrr mask mute_ind mask 7 6 5 4 3 2 1 0 address = 0011011 ovrl mask masks the ovrl from generating an interrupt 0 = the ovrl bit will not generate an interrupt 1 = the ovrl bit will generate an interrupt ovrr mask masks the ovrr from generating an interrupt 0 = the ovrr bit will not generate an interrupt 1 = the ovrr bit will generate an interrupt reserved mute_ind mask masks the mute_ind from generating an interrupt 0 = the mute_ind bit will not generate an interrupt 1 = the mute_ind bit will generate an interrupt table 52. interrupt status register src txcst- txub- txcs- rxcs- rxub- rxcs- rx- error int int int diff int bint error 7 6 5 4 3 2 1 0 address = 0011100 srcerror this bit will be set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample rate converter error register. this bit will remain high until the interrupt status register is read txcstint this bit will be set if a write to the transmitter channel status buffer was made while transmitter channel status bits were being copied from transmitter cs buffer to spdif transmit buffer txubint this bit will be set if the spdif transmit buffer is empty. this bit will remain high until the interrupt status register is re ad. txcsint this bit will be set if the transmitter channel status bit buffer has transmitted its block of channel status. this bit will re main high until the interrupt status register is read rxcsdiff this bit will be set if the receiver channel status a block is di fferent from the receiver channel status b clock. this bit wil l remain high until read but does not generate an interupt rxubint this bit will be set if the receiver user bit buffer has a new block or message. this bit will remain high until the interrupt status register is read. rxcsbint this bit will be set if a new block of channel status is read when rxbconf3 = 0 or if the channel status has changed when rxbconf3 = 1. this bit will remain high until the interrupt status register is read. rxerror this bit will be set if one of the aes3/spdif receiver interrupts is asserted and the host should immediately read the receiver error register. this bit will remain high until the interrupt status register is read.
adav803 preliminary technical data rev. pr g | page 40 of 54 table 53. interrupt status mask register srcerror txcstint txubint txcsbint rxubint rxcsbint rxerror mask mask mask mask res mask mask mask 7 6 5 4 3 2 1 0 address = 0011101 default value = 0x00 srcerror mask masks the srcerror bit from generating an interrupt 0 = the srcerror bit will not generate an interrupt 1 = the srcerror bit will generate and interrupt txcstint mask masks the txcstbint bit from generating an interrupt 0 = the txsctint bit will not generate an interrupt 1 = the txcstint bit will generate and interrupt txubint mask masks the txubint bit from generating an interrupt 0 = the txubint bit will not generate an interrupt 1 = the txubint bit will generate and interrupt rxubint mask masks the rxubint bit from generating an interrupt 0 = the rxubint bit will not generate an interrupt 1 = the rxubint bit will generate and interrupt rxcsbint mask masks the rxcsbint bit from generating an interrupt 0 = the rxcsbint bit will not generate an interrupt 1 = the rxcsbint bit will generate an interrupt rxerror mask masks the rxerror bit from generating an interrupt 0 = the rxerror bit will not generate an interrupt 1 = the rxerror bit will generate an interrupt table 54. mute and deemphasis register res res txmute res res src_deem1-0 res 7 6 5 4 3 2,1 0 address = 0011110 default value = 0x00 txmute mutes the aes3/spdif transmitter 0 = the transmitter is not muted 1 = the transmitter is muted src_deem1-0 selects the deemphasis filter for the input data to the sample rate converter 00 = no deemphasis 01 = 32 khz deemphasis 10 = 44.1 khz deemphasis 11 = 48 khz deemphasis
preliminary technical data adav803 rev. pr g | page 41 of 54 table 55. nonaudio preamble type register (read only) dts-cd non audio non audio non audio non audio res res res res preamble frame subframe_a subframe_b 7 6 5 4 3 2 1 0 address = 0011111 default value = 0x dts-cd preamble will be set if the dts-cd preamble is detect nonaudio frame this bit will be set if the data received through the ae s3/spdif receiver is nonaudio data according to the iec61937 standard or nonaudio data according to smpte337m nonaudio subframe_a this bit will be set if the data received through channel a of the aes3/spdif receiver is subframe nonaudio data according to smpte337m nonaudio subframe_b this bit will be set if the data received through channel b of the aes3/spdif receiver is subframe nonaudio data according to smpte337m table 56. receiver channel status buffer rcsb7 rcsb6 rcsb5 rcsb4 rcsb3 rcsb2 rcsb1 rcsb0 7 6 5 4 3 2 1 0 address = 0100000 to 0110111 this is the 24 byte receiver channel status buffer. the pro bit is stored at address location 0x20, bit 0. this buffer is read only if the channel status is not autobuffered between the receiver and transmitter. table 57. transmitter channel status buffer tcsb7 tcsb6 tcsb5 tcsb4 tcsb3 tcsb2 tcsb1 tcsb0 7 6 5 4 3 2 1 0 address = 0111000 to 1001111 this is the 24 byte transmitter channel status buffer. the pro bit is stored at address location 0x38, bit 0. this buffer is di sabled when autobuffering between the receiver and transmitter is enabled. table 58. receiver user bit buffer indirect address register rxubaddr07-rxubaddr00 7,6,5,4,3,2,1,0 address = 1010000 rxubaddr07-00 indirect address pointing to the address location in the receiver user bit buffer table 59. receiver user bit buffer data registe rxubdata07-rxubdata00 7,6,5,4,3,2,1,0 address = 1010001 rxubdata07-00 a read from this register will read 8 bits of user da ta from the receiver user bit buffer pointed to by rxubaddr7-0. this buffer can be written to when autobuffering of the user bits is enabled otherwise it is a read only buffer table 60. transmitter user bit buffer indirect address register txubaddr07-txubaddr00 7,6,5,4,3,2,1,0 address = 1010010 txubaddr07-00 indirect address pointing to the address location in the transmitter user bit buffer
adav803 preliminary technical data rev. pr g | page 42 of 54 table 61. transmitter user bit buffer data register txubdata07-txubdata00 7,6,5,4,3,2,1,0 address = 1010011 txubdata07-00 a write to this register will write 8 bits of user data to the transmit user bit buffer pointed to by txubaddr7-0. when user bit autobuffering is enabled this buffer is disabled. table 62. q subcode crc error status register (read only) res res res res res res qcrcerror qsub 7 6 5 4 3 2 1 0 address = 1010100 qcrcerror this bit will be set if the crc check of the q subcode fails. this bit will remain high but will not generate an interrupt. thi s bit will be cleared once the register is read. qsub this bit will be set if a q subcode has been read into the q subcode buffer table 63. q subcode buffe address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x55 address address address address control control control control 0x56 track number track number track number track number track number track number track number track number 0x57 index index index index index index index index 0x58 minute minute minute minute minute minute minute minute 0x59 second second second second second second second second 0x5a frame frame frame frame frame frame frame frame 0x5b zero zero zero zero zero zero zero zero 0x5c absolute minute absolute minute absolute minute absolute minute absolute minute absolute minute absolute minute absolute minute 0x5d absolute second absolute second absolute second absolute second absolute second absolute second absolute second absolute second 0x5e absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame
preliminary technical data adav803 rev. pr g | page 43 of 54 table 64. datapath control register 1 src1 src0 rec2 rec1 rec0 auxo2 auxo1 auxo0 7 6 5 4 3 2 1 0 address = 1100010 src1-0 datapath source select for sample rate converter(src) 00 = adc 01 = dir 10 = playback 11 = auxiliary in rec2-0 datapath source select for record output port 000 = adc 001 = dir 010 = playback 011 = auxiliary in 100 = src auxo2-0 datapath source select for auxiliary output port 000 = adc 001 = dir 010 = playback 011 = auxiliary in 100 = src table 65. datapath control register 2 res res dac2 dac1 dac0 dit2 dit1 dit0 7 6 5 4 3 2 1 0 address = 1100011 dac2-0 datapath source select for dac 000 = adc 001 = dir 010 = playback 011 = auxiliary in 100 = src dit2-0 datapath source select for dit 000 = adc 001 = dir 010 = playback 011 = auxiliary in 100 = src
adav803 preliminary technical data rev. pr g | page 44 of 54 table 66. dac control register 1 dr_all dr_dig chsel1 chsel0 pol1 pol0 muter mutel 7 6 5 4 3 2 1 0 address = 1100100 dr_all hard reset and powerdown 0 = normal, output pins go to v ref level 1 = hard reset & low power, output pins go to agnd dr_all dac digital reset 0 = normal 1 = reset all except registers chsel1-0 dac channel select 00 = normal left-right 01 = both right 10 = both left 11 = swapped, right-left pol1-0 dac channel polarity 00 = both positive 01 = left negative 10 = right negative 11 = both negative muter mute right channel 0 = normal 1 = mute mutel mute left channel 0 = normal 1 = mute table 67. dac control register 2 res res dmclk1 dmclk0 dfs dfs0 deem1 deem0 7 6 5 4 3 2 1 0 address = 1100101 dmclk1-0 dac mclk divider 00 = mclk 01 = mclk/1.5 10 = mclk/2 11 = mclk/3 dfs1-0 dac interpolator select 00 = 8 (mclk = 256 f s ) 01 = 4 (mclk = 128 f s ) 10 = 2 (mclk = 64 f s ) 11 = reserved deem1-0 dac de-emphasis select 00 = none 01 = 44.1 khz 10 = 32 khz 11 = 48 khz
preliminary technical data adav803 rev. pr g | page 45 of 54 table 68. dac control register 3 res res res res res zfvol zfdata zfpol 7 6 5 4 3 2 1 0 address = 1100110 zfvol dac zero flag on mute and zero volume 0 = enabled 1 = disabled zfdata dac zero flag on zero data disable 0 = enabled 1 = disabled zfpol dac zero flag polarity 0 = active high 1 = active low table 69. dac control register 4 res intrpt zerosel1 zerosel0 res res res res 7 6 5 4 3 2 1 0 address = 1100111 intrpt this bit selects the functionality of the zerol/int pin 0 = the pin functions as a zerol flag pin 1 = the pin functions as an interrupt pin zerosel1-0 these bits control the functionality of the zeror pin when the zerol/int pin is used as an interrupt 00 = the pin functions as a zeror flag pin 01 = the pin functions as a zerol flag pin 10 = the pin is asserted when either the left or right channel is zero 10 = the pin is asserted when both the left and right channels are zero table 70. dac left volume register dvoll7 dvoll6 dvoll5 dvoll4 dvoll3 dvoll2 dvoll1 dvoll0 7 6 5 4 3 2 1 0 address = 1101000 dvoll7-0 dac left channel volume control 1111111 = 0dbfs 1111110 = -0.375dbfs 0000000 = -95.625dbfs table 71. dac right volume register dvolr7 dvolr6 dvolr5 dvolr4 dvolr3 dvolr2 dvolr1 dvolr0 7 6 5 4 3 2 1 0 address = 1101001 dvoll7-0 dac right channel volume control 1111111 = 0dbfs 1111110 = -0.375dbfs 0000000 = -95.625dbfs
adav803 preliminary technical data rev. pr g | page 46 of 54 table 72. dac left peak volume register res res dlp5 dlp4 dlp3 dlp2 dlp1 dlp0 7 6 5 4 3 2 1 0 address = 1101010 dlp5-0 dac left channel peak volume detection 000000 = 0dbfs 000001 = -1dbfs 111111 = -63dbfs table 73. dac right peak volume register res res drp5 drp4 drp3 drp2 drp1 drp0 7 6 5 4 3 2 1 0 address = 1101011 drp5-0 dac right channel peak volume detection 000000 = 0dbfs 000001 = -1dbfs 111111 = -63dbfs table 74. adc left channel pga gain register res res agl5 agl4 agl3 agl2 agl1 agl0 7 6 5 4 3 2 1 0 address = 1101100 agl5-0 pga left channel gain control 000000 = 0 db 000001 = +0.5 db ........... 101111 = +23.5 db 110000 = +24 db ........... 111111 = +24 db table 75. adc right channel pga gain register res res agr5 agr4 agr3 agr2 agr1 agr0 7 6 5 4 3 2 1 0 address = 1101101 agr5-0 pga right channel gain control 000000 = 0 db 000001 = +0.5 db ........... 101111 = +23.5 db 110000 = +24 db ........... 111111 = +24 db
preliminary technical data adav803 rev. pr g | page 47 of 54 table 76. adc control register 1 amc hpf pwrdwn and_pd muter mutel plpd prpd 7 6 5 4 3 2 1 0 address = 1101110 amc adc modulator clock 0 = adc mclk/2 (128 f s ) 1 = adc mclk/4 (64 f s ) hpf high pass filter enable 0 = normal 1 = hpf enabled pwrdwn adc powerdown 0 = normal 1 = powerdown ana_pd adc analog section powedown 0 = normal 1 = powedown muter mute adc right channel 0 = normal 1 = muted mutel mute adc left channel 0 = normal 1 = muted plpd pga left powerdown 0 = normal 1 = powerdown prpd pga right powerdown 0 = normal 1 = powerdown table 77. adc control register 2 res res res buf_pd res res mcd1 mcd0 7 6 5 4 3 2 1 0 address = 1101111 buf_pd reference buffer powerdown control 0 = normal 1 = powerdown mcd1-0 adc master clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 1 table 78. adc left volume register avoll7 avoll6 avoll5 avoll4 avoll3 avoll2 avoll1 avoll0 7 6 5 4 3 2 1 0 address = 1110000 avoll7-0 adc left channel volume control 1111111 = 1.0 (0dbfs) 1111110 = 0.996 (-0.00348dbfs) 1000000 = 0.5 (-6dbfs) 0111111 = 0.496 (-6.09dbfs) 0000000 = 0.0039 (-48.18dbfs)
adav803 preliminary technical data rev. pr g | page 48 of 54 table 79. adc right volume register avolr7 avolr6 avolr5 avolr4 avolr3 avolr2 avolr1 avolr0 7 6 5 4 3 2 1 0 address = 1110001 avolr7-0 adc right channel volume control 1111111 = 1.0 (0dbfs) 1111110 = 0.996 (-0.00348dbfs) 1000000 = 0.5 (-6dbfs) 0111111 = 0.496 (-6.09dbfs) 0000000 = 0.0039 (-48.18dbfs) table 80. adc left peak volume register res res alp5 alp4 alp3 alp2 alp1 alp0 7 6 5 4 3 2 1 0 address = 1110010 alp5-0 adc left channel peak volume detection 000000 = 0dbfs 000001 = -1dbfs 111111 = -63dbfs table 81. adc right peak volume register res res arp5 arp4 arp3 arp2 arp1 arp0 7 6 5 4 3 2 1 0 address = 1110011 arp5-0 adc right channel peak volume detection 000000 = 0dbfs 000001 = -1dbfs 111111 = -63dbfs table 82. pll control register 1 res res mclkodiv plldiv pll2pd pll1pd xtlpd sysclk3 7 6 5 4 3 2 1 0 address = 1110100 mclkodiv divide input mclk by 2 to generate mclko 0 = disabled 1 = enabled plldiv divide xin by 2 to generate the pll master clock 0 = disabled 1 = enabled pll2pd powerdown pll2 0 = normal 1 = powerdown pll1pd powerdown pll1 0 = normal 1 = powerdown xtlpd powerdown xtal oscillator 0 = normal 1 = powerdown sysclk3 clock output for sysclk3 0 = 512 f s 1 = 256 f s
preliminary technical data adav803 rev. pr g | page 49 of 54 table 83. pll control register 2 fs2-1 fs2-1 sel2 doub2 fs1-1 fs1-0 sel1 doub1 7 6 5 4 3 2 1 0 address = 1110101 fs2_1-0 sample rate select for pll2 00 = 48 khz 01 = reserved 10 = 32 khz 11 = 44.1 khz sel2 oversample ratio select for pll2 0 = 256 f s 1 = 384 f s doub2 double selected sample rate on pll2 0 = disabled 1 = enabled fs1-0 sample rate select for pll1 00 = 48 khz 01 = reserved 10 = 32 khz 11 = 44.1 khz sel1 oversample ratio select for pll1 0 = 256 f s 1 = 384 f s doub1 double selected sample rate on pll1 0 = disabled 1 = enabled
adav803 preliminary technical data rev. pr g | page 50 of 54 table 84 .internal clocking control register 1 dclk2 dclk1 dclk0 aclk2 aclk1 aclk0 iclk2-1 iclk2-0 7 6 5 4 3 2 1 0 address = 1110110 dclk2-0 dac clock source select 000 = xin 001 = mclki 010 = pllint1 011 = pllint2 100 = dir pll (512 f s ) 101 = dir pll (256 f s ) 110 = xin 111 = xin aclk2-0 adc clock source select 000 = xin 001 = mclki 010 = pllint1 011 = pllint2 100 = dir pll (512 f s ) 101 = dir pll (256 f s ) 110 = xin 111 = xin iclk2 source selector for internal clock iclk2 00 = xin 01 = mclki 10 = pllint1 11 = pllint2
preliminary technical data adav803 rev. pr g | page 51 of 54 table 85. internal clocking control register 2 res res res iclk1-1 iclk1-0 pll2int1 pll2int0 pll1int 7 6 5 4 3 2 1 0 address = 1110111 iclk1-0 source selector for internal clock iclk1 00 = xin 01 = mclki 10 = pllint1 11 = pllint2 pll2int1-0 pll2 internal selector (see figure 18) 00 = fs2 01 = fs2/2 10 = fs3 11 = fs3/2 pll1int pll1 internal selector 0 = fs1 1 = fs1/2 table 86. pll clock source register pll1_source pll2_source res res res res res res 7 6 5 4 3 2 1 0 address = 1111000 pll1_source selects the clock source for pll1 0 = xin 1 = mclki pll2_source selects the clock source for pll2 0 = xin 1 = mclki table 87. pll output enable register res res res dirin_pin res sysclk1 sysclk2 sysclk3 7 6 5 4 3 2 1 0 address = 1111010 dirin_pin this bit determines the input levels of the dirin pin 0 = the dirin will accept input signals down to 200mv according to aes3 requirements 1 = the dirin will accept input signals as defined in table 13 sysclk1 enables the sysclk1 output 0 = enabled 1 = disabled sysclk2 enables the sysclk2 output 0 = enabled 1 = disabled sysclk3 enables the sysclk3 output 0 = enabled 1 = disabled
adav803 preliminary technical data rev. pr g | page 52 of 54 table 88. alc control register 1 fssel1-0 gaincntr1-0 recmode1-0 limdet alcen 7,6 5,4 3,2 1 0 address = 1111011 default = 0x00 these bits should equal the sample rate of the adc fssel1-0 00 = 96 khz 01 = 48 khz 10 = 32 khz 11 = reserved these bits determine the limit of the counter used in limited recovery mode gaincntr1-0 00 = 3 01 = 7 10 = 15 11 = 31 recmode1-0 these bits determine which recovery mode is used by the alc section 00 = no recovery 01 = normal recovery 10 = limited recovery 11 = reserved limdet limit detect mode 0 = alc is used when either channel exceeds the set limit 1 = alc is used only when both channels exceed the set limit alcen alc enable 0 = disable alc 1 = enable alc table 89. alc control register 2 res recth1-0 atkth1-0 rectime1-0 atktime 7 6,5 4,3 2,1 0 address = 1111100 default = 0x52 recth1-0 recovery threshold 00 = -2 db 01 = -3 db 10 = -4 db 11 = -6 db atkth1-0 attack theshold 00 = 0 db 01 = -1 db 10 = -2 db 11 = -4 db rectime1-0 recovery time selection 00 = 32 ms 01 = 64 ms 10 = 128 ms 11 = 256 ms atktime attack timer selection 0 = 1 ms 1 = 4 ms
preliminary technical data adav803 rev. pr g | page 53 of 54 table 90. alc control register 3 alc reset 7,6,5,4,3,2,1,0 address = 1111101 default = 0x00 alc reset a write to this register will restart the alc operation. the value written to this register is irrelevant. a read from this register will give the gain reduction factor.
adav803 preliminary technical data rev. pr g | page 54 of 54 outline dimensions figure 40. 64-lead plastic quad flatpack [lqfp] (st-64) dimensions shown in inches and (millimeters) ordering guide model temperature range control interface dac outputs package options ADAV803AST ?40c to +85c i 2 c single-ended st-64 ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners.

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